For several years, commercially available personal computers of the type commonly referred to as IBM compatible have typically used a standard system bus design commonly referred to as the Industry Standard Architecture (ISA). The ISA specification provides for twentyfour memory address lines. Now, systems are being introduced which utilize a system bus design which is an enhanced version of the ISA approach, commonly referred to as the Extended Industry Standard Architecture (EISA). The EISA standard provides for thirty-two address lines.
Existing circuit boards designed for use with the ISA standard can be used with an EISA system, but look at only the twenty-four least significant bits of the thirty-two EISA address lines, and thus ignore the eight most significant address bits. Consequently, where an ISA device, which is designed to respond to a particular combination of the twenty-four least significant bits and thus a unique address under the ISA standard, is used in an EISA system, it could potentially respond to several EISA memory addresses which have the same twenty-four least significant bits but different combinations of the eight most significant bits. An ISA device which responds to multiple EISA addresses in this manner could cause errors.
An integrated circuit is commercially available and can be used to control an EISA system bus. This integrated circuit produces certain control signals which are intended exclusively for use by ISA devices and which could thus be suppressed if an EISA address was outside the range of normal ISA addresses, but the design of the integrated circuit happens to be such that it does not do this and thus presents the potential for errors of the type discussed above. Of course, it would be possible to use, instead of this integrated circuit, a custom circuit made of discrete components and performing the same function, but this approach would involve significant additional cost, space and power consumption.
It is therefore an object of the present invention to provide a way of facilitating use of ISA devices in association with this EISA integrated circuit in a manner ensuring system operation free of errors.
The objects and purposes of the invention are met, for a system which includes first and second control lines and a plurality of address lines, by providing a method and apparatus which involve supplying an address to the address lines and a control signal to one of the control lines, monitoring the address lines and control lines, responding to detection of the control signal on the second control line by respectively effecting and inhibiting application of the control signal to the first control line when the address on the address lines is respectively within and outside a predetermined group of addresses, and responding to the occurrence of the control signal on the first control line by applying the control signal to the second control line regardless of the address on the address lines.